1. Field of the Invention
The present invention relates to an orthogonal code generation apparatus, a scrambling code generation apparatus, and a portable radio terminal using such apparatus. More particularly, the present invention relates to an orthogonal code generation apparatus generating an orthogonal code used in the spreading or despreading operation of transmission data or reception data, a scrambling code generation apparatus generating a scrambling code used in the scrambling operation of transmission data, and a portable radio terminal including such a code generation apparatus in digital radio communication.
2. Description of the Background Art
In the digital radio communication method such as the CDMA (Code Division Multiple Access) method used in mobile communication systems, a double spreading method set forth below is employed.
As to the uplink transmitting data from a portable radio terminal to a base station, a two-stage operation is carried out at the portable radio terminal. More specifically, digital data (symbol data) to be transmitted is subjected to a spreading operation with an orthogonal code, and then scrambled with a scrambling code.
The spreading operation of the transmission data (symbol data) with an orthogonal code is employed in order to transmit more data. In the case where symbol data of a plurality of channels are multiplexed at the terminal to be transmitted to the base station through one channel, data transmission for the plurality of channels is possible at a rate higher than the maximum transmission rate of one channel by applying a spreading operation on the symbol data of the plurality of channels with a plurality of corresponding orthogonal code sequences (sequence of codes each having a time width smaller than that of symbol), and then multiplexing the obtained transmission data (chip data) of the plurality of channels.
Such transmission data (chip data) is scrambled with a scrambling code inherent to each user (terminal) for identifying each user, and then transmitted to the base station.
As to the downlink transmitting data from the base station to a portable radio terminal, a two-stage operation is carried out at the base station. More specifically, digital data (symbol data) to be transmitted is subjected to a spreading operation with an orthogonal code, and then scrambled with a scrambling code.
In order to identify the channel, transmission data (symbol data) is subjected to a spreading operation with an orthogonal code sequence (sequence of codes each having a time width shorter than that of symbol) for each channel.
The obtained transmission data (chip) is scrambled with a scrambling code inherent to each cell (base station) for identifying each cell, and then transmitted to a portable radio terminal.
Although respective objects differ, the two-stage operation of spreading and scrambling is carried out using two types of codes, i.e., an orthogonal code and scrambling code, at the uplink and downlink. Thus, this method is called a double spreading method.
A portable radio terminal of digital radio communication employing this double spreading method must be configured as set forth below.
In order to transmit data to the base station, an orthogonal code generation apparatus generating a sequence of orthogonal codes for the spreading operation of transmission data (symbol data) is required. Also, a scrambling code generation apparatus generating a sequence of scrambling codes for the scrambling operation of transmission data (chip data) is required.
In order to receive data subjected to the aforementioned spreading and scrambling operations at the base station, a scrambling code generation apparatus generating a sequence of scrambling codes for the descrambling operation of reception data (chip data) as well as an orthogonal code generation apparatus generating a sequence of orthogonal codes for the inverse spreading operation of reception data (chip data) are required.
Although the same type of orthogonal code generation apparatus can be used for the spreading operation of transmission data and the inverse spreading operation of reception data, different types of scrambling code generation apparatuses are used in the scrambling operation of transmission data and the descrambling operation of reception data for reasons of circuit configuration.
An orthogonal code generation apparatus employed in the spreading operation of transmission data and reception data at a portable radio terminal will be described hereinafter.
An orthogonal code generation apparatus is configured to have a plurality of orthogonal code sequences, each formed of a plurality of bits (a multi-bit period), entirely prestored in a memory, and generate an address of data to be read out from the memory, based on a sequence number specifying an orthogonal code sequence to be generated and a location number specifying the location of an orthogonal code to be generated from the specified orthogonal code sequence, and then read out the addressed data from the memory for output as the orthogonal code.
The output orthogonal code is multiplied (exclusive OR operation) by the transmission digital data (symbol data). Thus, the transmission digital data is subjected a spreading operation.
FIG. 14 is a block diagram showing an example of a conventional orthogonal code generation apparatus. The orthogonal code generation apparatus of FIG. 14 basically includes an address generator 10a, a memory 10b, and a parallel-serial conversion circuit 10c. 
Referring to FIG. 14, a plurality of sequences of orthogonal codes are prestored in memory 10b. Each sequence has a multi-bit period (for example, in the CDMA standard, variable within the range of the period of 256 bits at most).
The sequence number specifying a sequence of orthogonal codes to be used in the spreading operation with the transmission digital data among the plurality of sequences of orthogonal codes is applied from a control circuit not shown to address generator 10a. In general, the specified orthogonal code sequence of a multi-bit period is divided into unit data each of a plurality of bits (for example, the unit of 4 bits) to be read out from memory 10b. Therefore, a location number specifying the head bit location of each data is also applied from a control circuit not shown to address generator 10a. 
Address generator 10a generates an address and a memory access control signal to read out from memory 10b the specified data of a plurality of bits from the specified sequence of orthogonal codes based on the applied sequence number and location number. The generated address and memory access control signal are provided to memory 10b. 
Data of a plurality of bits from the sequence of orthogonal codes identified by the applied address are read out together at one time from memory 10b to be applied to parallel-serial conversion circuit 10c. Parallel-serial conversion circuit 10c converts the data of a plurality of bits read out from memory 10b into a train of bits in series. The data is output as a sequence of orthogonal codes. The output orthogonal code sequence is subjected to a spreading operation with the transmission data.
A scrambling code generation apparatus employed in the scrambling operation of transmission data at a portable radio terminal will be described hereinafter.
The scrambling code generation apparatus is configured to have an initial value inherent to the relevant terminal set in a shift register configured based on a predetermined generating polynomial. In order to establish timing with the generation of scrambling codes for descrambling in the base station at the reception side, a shift operation is effected for a predetermined number of times based on the initial value. Then, codes are continuously output as a sequence of scrambling codes.
The output scrambling code sequence is multiplied by the transmission digital data (chip data). Thus, transmission digital data is scrambled.
FIG. 15 is a block diagram showing an example of a conventional scrambling code generation apparatus. FIG. 15 is particularly directed to a scrambling code generation apparatus configured to generate a scrambling code sequence by a generating polynomial set forth below.f(X)=X4+X2+1
The scrambling code generation apparatus of FIG. 15 includes a shift register basically formed of four cascade-connected registers 11, 12, 13 and 14. Selectors 15, 16, 17 and 18 are provided at the preceding stages of corresponding registers.
An initial value buffer 19 stores initial values Ri3, Ri2, Ri1 and Ri0 that will be described afterwards. Initial value buffer 19 is implemented with, for example, a memory, a register, or the like.
Each of selectors 15-18 responds to a control signal applied from a control circuit not shown to select an output Rs from the preceding-stage register or a corresponding initial value Ri stored in initial value buffer 19 to provide the selected value to the D input of the register of the next stage.
More specifically, selector 15 selects either an output from an exclusive OR circuit 20 or initial value Ri3, and sets the selected value in register 11 as input D3.
Selector 16 selects output Rs3 of the preceding-stage register 11 or initial value Ri2, and sets the selected value in register 12 as input D2. Output Rs2 of register 12 is applied to one input of register 17 and also fed back to one input of exclusive OR circuit 20.
Selector 17 selects output Rs2 of the preceding-stage register 12 or initial value Ri1, and sets the selected value in register 13 as input D1.
Selector 18 selects output Rs1 of the preceding-stage register 13 or initial value Ri0, and sets the selected value in register 14 as input D0. Output Rs0 of register 14 is output (spreading operated) from the shift register as a scrambling code, and also fed back to the other input of exclusive OR circuit 20.
The operation of scrambling code generation by the scrambling code generation apparatus of FIG. 15 will be described here. Although a shift register is configured including 25 stages of registers according to the standard of the current digital radio communication (for example, the digital radio communication of the W (Wideband)-CDMA method recently developed), a simplified shift register formed of registers of 4 stages is taken as an example for description hereinafter for the sake of simplifying the drawings.
Initial values Ri3, Ri2, Ri1 and Ri0 (excluding the case of all 0) inherent to the relevant terminal are set in initial value buffer 19. The initial values are loaded via corresponding selectors 15-18 to the four registers 11-14, respectively. Then, a shift operation is effected based on the loaded initial values, while scrambling code Rs0 is sequentially output from register 14. Registers 11-14 are set with inputs D3, D2, D1 and D0, respectively, represented by the following expression for each one shift operation.D3←Rs2⊕Rs0D2←Rs3D1←Rs2D0←Rs1  [Expression 1]
This operation can be represented as below using a matrix. The addition employed in the following operation (including matrix operation) is modulo 2 addition.
                              [                                                                      D                  3                                                                                                      D                  2                                                                                                      D                  1                                                                                                      D                  0                                                              ]                =                              [                                                            0                                                  1                                                  0                                                  1                                                                              1                                                  0                                                  0                                                  0                                                                              0                                                  1                                                  0                                                  0                                                                              0                                                  0                                                  1                                                  0                                                      ]                    ⁡                      [                                                                                Rs                    3                                                                                                                    Rs                    2                                                                                                                    Rs                    1                                                                                                                    Rs                    0                                                                        ]                                              [                  Expression          ⁢                                          ⁢          2                ]            
Respective values in registers 11-14 after being shifted once from respective loading of the above four initial values into registers 11-14 are represented by the matrix below.
                              [                                                                      D                  3                                                                                                      D                  2                                                                                                      D                  1                                                                                                      D                  0                                                              ]                =                              [                                                            0                                                  1                                                  0                                                  1                                                                              1                                                  0                                                  0                                                  0                                                                              0                                                  1                                                  0                                                  0                                                                              0                                                  0                                                  1                                                  0                                                      ]                    ⁡                      [                                                                                Ri                    3                                                                                                                    Ri                    2                                                                                                                    Ri                    1                                                                                                                    Ri                    0                                                                        ]                                              [                  Expression          ⁢                                          ⁢          3                ]            
Respective values in registers 11-14 after being shifted twice is represented by the following matrix.
                                                                        [                                                                                                    D                        3                                                                                                                                                D                        2                                                                                                                                                D                        1                                                                                                                                                D                        0                                                                                            ]                            =                            ⁢                                                                    [                                                                                            0                                                                          1                                                                          0                                                                          1                                                                                                                      1                                                                          0                                                                          0                                                                          0                                                                                                                      0                                                                          1                                                                          0                                                                          0                                                                                                                      0                                                                          0                                                                          1                                                                          0                                                                                      ]                                    ⁡                                      [                                                                                            0                                                                          1                                                                          0                                                                          1                                                                                                                      1                                                                          0                                                                          0                                                                          0                                                                                                                      0                                                                          1                                                                          0                                                                          0                                                                                                                      0                                                                          0                                                                          1                                                                          0                                                                                      ]                                                  ⁡                                  [                                                                                                              Ri                          3                                                                                                                                                              Ri                          2                                                                                                                                                              Ri                          1                                                                                                                                                              Ri                          0                                                                                                      ]                                                                                                        =                            ⁢                                                [                                                                                    1                                                                    0                                                                    1                                                                    0                                                                                                            0                                                                    1                                                                    0                                                                    1                                                                                                            1                                                                    0                                                                    0                                                                    0                                                                                                            0                                                                    1                                                                    0                                                                    0                                                                              ]                                ⁡                                  [                                                                                                              Ri                          3                                                                                                                                                              Ri                          2                                                                                                                                                              Ri                          1                                                                                                                                                              Ri                          0                                                                                                      ]                                                                                        [                  Expression          ⁢                                          ⁢          4                ]            
In general, respective values D3(t), D2(t), D1(t), and D0(t) in registers 11-14 subjected to a shift operation t times after the loading of respective initial values into registers 11-14 are represented by the following matrix.
                              [                                                                      D                                      3                    ⁢                                          (                      t                      )                                                                                                                                            D                                      2                    ⁢                                          (                      t                      )                                                                                                                                            D                                      1                    ⁢                                          (                      t                      )                                                                                                                                            D                                      0                    ⁢                                          (                      t                      )                                                                                                    ]                =                                            [                                                                    0                                                        1                                                        0                                                        1                                                                                        1                                                        0                                                        0                                                        0                                                                                        0                                                        1                                                        0                                                        0                                                                                        0                                                        0                                                        1                                                        0                                                              ]                        t                    ⁡                      [                                                                                Ri                    3                                                                                                                    Ri                    2                                                                                                                    Ri                    1                                                                                                                    Ri                    0                                                                        ]                                              [                  Expression          ⁢                                          ⁢          5                ]            
Starting from the load of initial values into registers 11-14, the value set in register 14 is determined by repeating a shift operation, whereby code Rs0 will sequentially generated.
It is to be noted that, according to the standard of the current digital radio communication (for example W-CDMA), the code generated continuously from each shift operation starting from the initial value is not directly used as the scrambling code. As mentioned before, in order to establish timing with the reception side, it is defined by the standard to output the register value as a scrambling code after a shift operation is effected t times (for example, 100 times) from the loading of initial values to registers 11-14. In other words, a scrambling code is not generated until a shift operation is carried out 100 times from the load of the initial values. A shift operation of 100 times is time consuming (particularly when there are many stages in the shift register).
By using the above indicated matrix that obtains a register value after t shift operations, the desired register value can be obtained through calculation even if the shift register does not actually perform a shift operation t times.
If it is defined to initiate generation of a scrambling code sequence from a register value after a shift operation is carried out 100 times from the loading of initial values according to the digital radio communication standard, the values D3(100), D2(100), D1(100) and D0(100) in registers 11-14 after a shift operation is effected 100 times can be obtained at once through the calculation of the following expression.
                                                                        [                                                                                                    D                                                  3                          ⁢                                                      (                            100                            )                                                                                                                                                                                                  D                                                  2                          ⁢                                                      (                            100                            )                                                                                                                                                                                                  D                                                  1                          ⁢                                                      (                            100                            )                                                                                                                                                                                                  D                                                  0                          ⁢                                                      (                            100                            )                                                                                                                                              ]                            =                            ⁢                                                                    [                                                                                            0                                                                          1                                                                          0                                                                          1                                                                                                                      1                                                                          0                                                                          0                                                                          0                                                                                                                      0                                                                          1                                                                          0                                                                          0                                                                                                                      0                                                                          0                                                                          1                                                                          0                                                                                      ]                                    100                                ⁡                                  [                                                                                                              Ri                          3                                                                                                                                                              Ri                          2                                                                                                                                                              Ri                          1                                                                                                                                                              Ri                          0                                                                                                      ]                                                                                                        =                            ⁢                                                [                                                                                    0                                                                    0                                                                    1                                                                    0                                                                                                            0                                                                    0                                                                    0                                                                    1                                                                                                            1                                                                    0                                                                    1                                                                    0                                                                                                            0                                                                    1                                                                    0                                                                    1                                                                              ]                                ⁡                                  [                                                                                                              Ri                          3                                                                                                                                                              Ri                          2                                                                                                                                                              Ri                          1                                                                                                                                                              Ri                          0                                                                                                      ]                                                                                        [                  Expression          ⁢                                          ⁢          6                ]            
The matrix of determining each register value after 100 shift operations of this expression can be segmented into M matrixes M3(100), M2(100), M1(100), and M0(100) for respective rows as indicated by the following expression.M3(100)=[0 0 1 0]M2(100)=[0 0 0 1]M1(100)=[1 0 1 0]M0(100)=[0 1 0 1]  [Expression 7]
By obtaining and storing these matrixes in advance, application of initial values for each user allows respective values of registers 11-14 after 100 shift operations to be calculated immediately. Then, by continuing the subsequent shift operation of the shift register, a sequence of scrambling codes following the shift operation of 100 times from the loading of the initial values can be sequentially generated.
FIG. 16 is a block diagram showing a scrambling code generation apparatus that can immediately determine a register value after, for example, 100 shift operations, from loading of the initial values to initiate generation of a sequence of scrambling codes.
In FIG. 16, the structure of the shift register including registers 11-14, selectors 15-18 and exclusive OR circuit 20 is similar to that of the shift register shown in FIG. 15. Therefore, description thereof will not be repeated.
According to the circuit configuration of FIG. 16, an arithmetic circuit 21 includes a memory or register in which M matrixes M3(100), M2(100), M1(100), and M0(100) to determine respective register values after 100 shift operations. Alternatively, arithmetic circuit 21 is implemented with the hardware of logic gates combined so as to generate these M matrixes. An initial value buffer 22 is applied with initial values Ri=[Ri3, Ri2, Ri1, Ri0] inherent to the relevant terminal. Initial value buffer 22 is implemented with, for example, a memory, a register or the like.
Arithmetic circuit 21 multiplies the above M matrixes by the initial values Ri applied to initial value buffer 22 to calculate values Ro3, Ro2, Ro1, and Ro0 of registers 1-4 after 100 shift operations.
The obtained register values are loaded to corresponding registers 11-14 via selectors 15-18, respectively, at a predetermined timing. By performing a shift operation of the shift register thereafter, output code Rs0 of register 14 subsequent to the shift operation of 100 times can be sequentially output as a sequence of scrambling codes. The output scrambling code sequence is used in the scrambling operation with the transmission data.
The conventional orthogonal code generation apparatus of FIG. 14 has all the orthogonal code sequences that will be specified stored in memory 10b. This means that, when 16 sequences of orthogonal codes of the period of 16 bits, for example, are to be stored in memory 10b, the square of the bit period, i.e., 16×16 bits, is required for the storage capacity.
Since the required memory capacity generally corresponds to the square of the bit period of the orthogonal code sequence, the required memory capacity will increase significantly as the bit period of the orthogonal code sequence to be stored becomes longer. The circuit complexity of the orthogonal code generation apparatus will become higher significantly.
The conventional scrambling code generation apparatus of FIG. 16 has the problem that the circuit complexity of arithmetic circuit 21 is increased. Although a shift register of four stages of registers is taken as an example for the sake of simplification in the above description of FIG. 16, a shift register of many stages, for example 25 stages, is employed according to the current standard and specification. The circuit complexity of arithmetic circuit 21 will become greater in proportion to the number of stages of the shift register.